02/01/1997 09:00 AM
Computer Engineering
As the devices and lines shrink into the deep submicron range, it is more effective to insert the intermediate buffers rather than to widen the wires. Almost all existing timing driven floorplanning and placement algorithms and tools don\'t consider the option of buffer insertion, so many good solutions with smaller area and better routability may be unnecessarily excluded. In this paper, we propose a new methodology of floorplanning and placement where buffered trees are used to estimate the wiring delay. Instead of treating the delay as one of the objectives as done by most of the previous works, we formulate the Delay Bounded Minimum Buffered Tree (DBMB-tree) as follows: given a net and delay bounds associated with critical terminals, construct a tree with intermediate buffers inserted to minimize the total wiring length while satisfying the given delay bounds. Based on the Elmore delay model, we propose an efficient algorithm to construct DBMB-tree for floorplanning and placement. Experiment results show that using buffer insertion at the floorplanning and placement stage yields significantly better solutions in terms of both chip area and total wire length. Existing multi-objective floorplanning tools use weighted cost summation subject to user-defined constraints to evaluate the solution. It is difficult, if not impossible, to derive a set of weight values from the vaguely defined multiple objectives and the optimization results are very sensitive to the choice of the weight values. Multi-dimension cost vector is introduced to represent the cost value for each objective explicitly by H. Esbensen. We define the acceptance function in multiple dimensions based on the votes of invited experts, and order the objectives by their sensitivities. Multiple objectives are introduced gradually during the optimization process. The experiment results demonstrate the efficiency of the approach.
