12/01/1995 09:00 AM
Computer Engineering
In this paper, a new method named Dimension Reduction Technique (DRT) is presented for capacitance extraction of 3D multilayer and multiconductor interconnects. In this technique, a complex 3D problem is decomposed to a series of simpler 2D problems. Therefore, it results in dramatical savings in computing time and memory usage. Compared to FASTCAP, a field solver based on BEM with multipole acceleration and developed from MIT, DRT is generally an order of magnitude faster with significantly less memory usage. Based on this technique, accurate close-form formulae or data base can be generated efficiently for calculating the capacitances of some typical 3D structures of VLSI interconnect.
