UCSC-SOE-16-20: Characterization of Flip-Flop Designs at Subthreshold Voltages

Jeff Butera, Matthew Guthaus
12/13/2016 05:20 PM
Computer Engineering
As transistor sizes scale down, there is an increase in the power dissipation of digital circuits due to leakage and increased density. Subthreshold operation has become an efficient approach to decrease both the static and dynamic power dissipation of a circuit. Specifically, we are interested in the subthreshold behavior of flip-flop designs. In this paper we characterize the performance and power aspects of three master-slave flip-flop designs at near- and sub-threshold voltages. By analyzing the Clk-Q delay, setup time, and average power of a flip-flop, we provide insight into the performance and power information that is useful for subthreshold designers.