12/01/1996 09:00 AM
Electrical Engineering
Shorts and opens are the most common types of defects in today\'s CMOS integrated circuits. This dissertation focuses on opens that occur in transistor drain/source connections and in the interconnect wiring. Compared to prior research, a very efficient and the most accurate, in terms of taking all test invalidation mechanisms into account, fault simulator for opens in drain/source connections is presented. Results show the individual contributions of different test invalidation mechanisms. How interconnect opens can cause oscillations and sequential behavior is demonstrated for the first time. Necessary conditions for such behavior are likely to occur in many interconnect opens. A fault simulation algorithm for interconnect opens, which takes into account all known factors that can affect the behavior of an interconnect open, is presented. The estimated run-time for this algorithm is a constant multiple of the run-time required for stuck-at-fault simulation. Empirical evidence from test chips, which contain various floating-gate transistor structures, shows for the first time that the die surface can become a factor in determining the behavior of a floating wire created by an interconnect open.
