06/01/1996 09:00 AM
Computer Engineering
Integrated circuits (ICs) are continually increasing in complexity. As IC complexity increases, the cost of testing the IC also increases. As a result, IC designers are expending greater amounts of effort on designing the ICs to be more easily tested. Most of the work done in measuring the testability of ICs and modifying the ICs to improve testability has been focused at the schematic level. This dissertation defines a metric for measuring the testability of cells used in ICs at the physical design level. This testability metric takes into account the three major influences on testability: the physical design, the circuit schematic, and the methods used to test the circuit. IC designers can use this testability metric as a guide for modifying the physical design of logic cells to increase their testability. This dissertation shows that, for standard cell designs, designing the cells to be more testable will have a larger impact on the testability of the circuit than designing other parts of the circuit. Thus, the testability metric described here concentrates on the cells used in standard cell designs. This dissertation describes an implementation of the testability metric. This dissertation applies the metric to two cells from a standard cell library to demonstrate how cell testability can be used to guide the modification of the cell\'s physical design to improve its testability.
