06/01/1995 09:00 AM

Computer Engineering

This dissertation presents the new concept of chip/package co-design for clock networks. Constructing a large flat size clock network that achieves zero skew is very challenging in VLSI design. Two new concepts are presented in this dissertation: (1) Since the package layer has far smaller RC interconnect parameters than a chip layer, placing the global clock tree on the package layer can decrease the skew, delay and wire capacitance significantly. (2) Using tolerable skew constraints between sequentially adjacent registers in synchronous circuits can simplify the clock distribution and reduce the total wire length of the clock tree significantly. We proposed a new clock distribution scheme which partitions the clock network into two levels. First, the clock terminals are partitioned into a set of clusters. For each cluster, a local on- chip clock tree is used to distribute the clock signal from a locally inserted buffer to terminals inside this cluster. The clock signal is then distributed from the main clock driver to each of local buffers by means of a global clock tree, which is routed on the package layer. Flip chip area I/O connections are used to make the connections between the global clock tree and the on-chip local clock trees. Algorithms are proposed to construct a planar equal path length tree for the global clock tree. Since it is planar, the global clock tree can be embedded on a single package layer, reducing the delay and attenuation through vias as well as sensitivity to process variations. The global clock tree is further improved iteratively to reduce the total wire length while maintaining the tolerable skew constraints. The skew constrained cut-and-link tree plays a key role in the iterative refinement. A clock sizing technique is used to decrease the skew of the global clock tree if the tolerable skew constraints are not satisfied. The optimal clock sizing problem is solved by a least square minimization method. In addition, this dissertation investigates the delay bounded minimum Steiner tree problem. Delay bounded minimum Steiner tree can be used for the interconnect tree construction when the interconnect delay becomes significant. A new iterative algorithm is proposed to construct a delay bounded minimum Steiner tree. Notes:Ph.D. Thesis