Authors

Published On 03/01/1993 09:00 AM

Department Computer Engineering

Abstract The design of high speed digital VLSI circuits prefers that the clock net is routed on the metal layer with the smallest RC delay. This strategy not only avoids the difficulties of having different electrical parameters on different layers, but also eliminates the delay and attenuation of the clock signal through vias. The clock phase-delay is also decreased. In this paper, we present a novel algorithm, based on hierarchical max-min optimization, to construct a planar clock tree which can be embedded on a single metal layer. The clock tree achieves equal path length---the length of the path from the clock source to each clock terminal is exactly the same. In addition, the path length from the source to clock terminals is minimized. Some examples including industrial benchmarks have been tested and the results are promising. We further optimize the geometry of the clock tree to minimize both the skew and path delay of the clock signal while maintaining the planarity of the clock network. Some premilinary results are promising which achieve near zero skew by using SPICE simulation.

Download

UCSC-CRL-93-17