10/01/1991 09:00 AM
Computer Engineering
With the growing complexity of field programmable gate arrays (FPGA), there is the growing need for sophisticated design tools to provide higher level abstractions for managing large designs. It is not enough to be able to create large designs; it is also necessary to test and debug them. Debugging FPGA designs on the circuit board is an awkward task, since the designer can only access the input/output pins of the chip. XS provides the designer with the ability to simulate and debug circuit designs quickly, and with access to all internal nets. XS is a batch-mode, unit-delay, event-driven logic simulator written in Gnu C++ for verification of designs under the unix X-window environment. We exploit certain properties in XILINX XC2000/3000/4000 architectures to enhance the performance as well as the accuracy of the simulator. This report serves the dual purposes of being the USER GUIDE as well as documenting the development of XS.
