06/01/1991 09:00 AM
Computer Engineering
Traditional fault models for testing CMOS VLSI circuits do not take into account the actual mechanisms that precipitate faults. As a result, the failure modes of a circuit as predicted by these fault models may not reflect the realistic failure modes of the circuit. This thesis reports on the Carafe software which determines the realistic bridge faults of the CMOS circuit based on its layout. Each fault found by Carafe is assigned a relative probability based on the geometry of the fault site and defect distributions of the fabrication process. Carafe improves upon previous software in that it is easier to use, more robust, and more time and memory efficient so that larger circuits can be analyzed.
