04/01/1991 09:00 AM
Computer Engineering
We examine empirically the performance of multi- level logic minimization tools for a lookup table-based Field-Programmable Gate Array (FPGA) technology. The experiments are conducted by using the university tools *misII* for combinational logic minimization and *mustang* for state assignment, the industrial tools *xnfmap* for technology mapping, and *apr* for automatic placement and routing. We measure the quality of the multi-level minimization tools by the number of *routed* configurable logic blocks (CLBs) in the FPGA realization. We report three results: a) we have developed a new system to support rapid prototyping using FPGAs, b) there is a linear relationship between the number of literals and the number of *routed* CLBs, and c) in all but one of the 31 *MCNC-89* benchmark finite state machines, one-hot state assignment resulted in substantially less CLBs than any other state encoding method. These results are useful to those who prototype a design in FPGAs, and then transfer the design to a different technology (e.g., CMOS standard cell). It provides valuable information on the difference in performance of a design realized in different technologies.
