05/01/1991 09:00 AM
Computer Engineering
Many manufacturing defects in static CMOS circuits are not detected by tests generated using the traditional single stuck-at fault model. Many of these defects may be detected as increased propagation delay or as excessive quiescent power supply current (I_DDQ). In this paper we compare the costs of detecting probable manufacturing defects by the resulting excess I_DDQ with the costs of traditional logical testing methods.
