04/01/1997 09:00 AM
Computer Engineering
As devices and lines shrink into the deep submicron range, the propagation delay of signals can be effectively improved by repowering the signals using intermediate buffers placed within the routing trees. Almost no existing timing driven floorplanning and placement approaches consider the option of buffer insertion. As such, they may exclude solutions, particularly early in the design process, with smaller overall area and better routability. In this paper, we propose a new methodology in which buffered trees are used to estimate wire delay during floorplanning and placement. Instead of treating delay as one of the objectives, as done by the majority of previous work, we formulate the problem in terms of Delay Bounded Buffered Trees (DBB-tree). The DBB formulation is as follows: Given a net and delay bounds on critical sinks, construct a tree with intermediate buffers inserted to minimize both the total wiring length and the number of buffers while satisfying the given delay bounds. Based on the Elmore delay model, we propose an efficient algorithm to construct a DBB spanning tree for use during floorplanning and placement. Experimental results show that the algorithm is very effective. Using buffer insertion at the floorplanning and placement stage yields significantly better solutions in terms of both chip area and total wire length.
