10/01/1993 09:00 AM
Computer Engineering
The flip-chip technology for multi-chip modules provides area pads through solder bumps which are distributed over the entire chip surface. Clock skew has been identified as one of major limiting factors for high speed VLSI systems. We propose a two level clock routing scheme for a MCM-packaged VLSI system by making use of area pads and high connectivity of MCM substrate. The die is partitioned small isochronal regions with a area pad assigned for each bin. We implement the clock network of the MCM system in two levels. A global clock network with longer wires is routed on the MCM substrate which connects the clock source of the module to all clock area pads of dice. Inside every isochronous bin of a die, a delay-bounded clock tree is constructed from clock pad to clocked elements. Experimental results show this two level clock routing scheme dramatically reduces the clock wires and achieves high clocking performance of the whole MCM system.
