12/01/1991 09:00 AM
Computer Science
This thesis describes an automated *Built-In Self- Test* (BIST) technique for general sequential circuits. The technique replaces storage elements in a given circuit with self-test elements. These elements are then connected as a shift register, and used both to generate test patterns and to compress test responses. Benchmarks were run on a number of standard sequential benchmark circuits to determine single stuck-at fault coverage. The results of these tests indicate that the self-test techniques presented here obtain fault coverage similar to that of random test techniques.
