04/01/1991 09:00 AM
Computer Engineering
This report describes the tricks involved in simulating a chip containing a 1-transistor style dynamic RAM using the COSMOS switch-level simulator. The reader is assumed to be familiar with this style of dynamic RAM. The specifics are drawn from a variant of the Caltech Mosaic RAM as modified at UCSC, but most of the tricks generalize to other CMOS dRAMs. The appendix gives a minimal list of attribute labels for the Mosaic RAM.
