UCSC-CRL-90-66: PERFORMANCE EVALUATION OF BUFFERED SWITCHES IN PACKET SWITCHING NETWORKS WITH MESH TOPOLOGIES

12/01/1990 09:00 AM
Computer Science
The goal of this thesis is to evaluate the performance of buffered switches in regular mesh topology packet switching networks. The thesis consists of three parts. The first part presents a simulation model of a mesh topology packet switching network. The simulation results suggest that providing a small source and output buffer at switching nodes can significantly improve the total throughput of the network. We also investigate the performance of buffered switches in a Manhattan network, a particular case of mesh networks. We propose a design of a 2 X 2 packet switch and a routing protocol which limits to 3 the number of times a packet needs to be buffered in an arbitrary sized Manhattan network before reaching its destination. The second part presents an approximate method to compute the throughput, and average end-to-end delays in the network. This method is based on solving a system of recurrence equations using a fixed point iterative scheme. Comparison with the simulation results show that the approximations are sharp. The third part addresses blocking in tandem queues. Finite buffers can cause blocking in networks. The exact numerical solution of such networks very quickly becomes intactable due to the large state space. We study a speed-up technique to an approximate method for solving such networks. We find that our technique can speed-up the solution by an order of magnitude, especially for large networks. The major contributions of this thesis are: (1) an extensive simulation study which suggests that providing small buffers at the switching nodes can significantly improve the throughput in regular mesh topology networks; (2) proposed design of a packet switch and a routing protocol which limits the number of times a packet needs to be buffered in a Manhattan network; (3) analytical models to estimate the performance of regular mesh networks using both buffered and unbuffered packet switches; and (4) a study of a speed-up technique to one of the approximation methods for solving tandem queues with blocking.

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