UCSC-CRL-03-17: An Analysis of Detection Probabilities of Interconnect Opens

03/14/2004 09:00 AM
Computer Engineering
An interconnect break is a break that occurs in the interconnect wiring, which results in logic gate inputs being disconnected from the drivers and causes the wire to float. Interconnect breaks are the most common types of breaks in modern CMOS integrated circuits, so testing and detecting these breaks has become very important. This paper models the conditions required for stuck-at tests to detect interconnect breaks in a circuit. We do a worstcase analysis of the detection of these breaks and calculate the minimum length of a test vector required to detect such defects with a specified confidence level, using n-detection principles. To enhance the understanding of the faulty behavior of the circuit, this paper presents a statistical model with certain simplifying assumptions based on the length distribution of the wires surrounding the floating wire. From the model we compute the detection probabilities of such breaks and show that the worst case of detection is when the bias voltage is the logic threshold voltage.

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