UCSC-CRL-00-03: ROUTING OPTIMIZER FOR CROSS-TALK NOISE AVOIDANCE IN RESISTIVE VLSI INTERCONNECTIONS

12/01/1999 09:00 AM
Computer Engineering
At present, our ability to identify cross-talk noise violations in a VLSI chip routing far surpasses our ability to resolve them. This is primarily due to the inherent shortcomings of Manhattan routers. In addition, while there have been several attempts to solve the cross-talk noise avoidance routing problem over the past decade, none of them have taken into account the resistive nature of VLSI interconnections. In this paper we formulate and demonstrate the first routing optimizer for cross-talk noise avoidance in resistive VLSI interconnections. Our new approach specifically accounts for the resistive nature of VLSI interconnections. In addition, our new approach avoids the shortcomings of Manhattan routers by taking advantage of the greater flexibility and power of topological routing. Finally, we demonstrate that our new approach is practical and computationally efficient.

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